1. Field of the Invention
The present invention relates to a plasma display panel, and more particularly to a plasma display panel that is adapted for reducing power consumption and calorific value.
2. Description of the Related Art
A plasma display panel (hereinafter ‘PDP’) excites phosphorus by using ultraviolet ray to emit light, thereby displaying a picture, wherein the ultraviolet ray is generated when an inert gas mixture such as He+Xe, Ne+Xe and He+Xe+Ne is discharged. PDP picture quality has improved due to recent technology development, and they are now thinner and larger than in the past.
In order to realize the gray level of a picture, the PDP is time-dividedly driven by dividing one frame into several sub-fields, each having different light emission values from one another. Each sub field can be further divided into a reset period, to initialize a full screen; an address period, to select scan lines and select discharge cells from the selected scan lines; and a sustain period, to realize gray levels in accordance with the number of discharges. For example, in displaying a picture with 256 gray levels, the frame period (16.67 ms) corresponding to 1/60 second as in FIG. 1 is divided into 8 sub-fields (SF1 to SF8). Each of the 8 sub-fields (SF1 to SF8), as described above, is divided into the reset period, the address period and the sustain period. The reset period and the address period of each sub-field are the same for each sub-field, while the sustain periods differ in that the number of sustain pulses allotted to each increases at the rate of 2n (n=0, 1, 2, 3, 4, 5, 6, 7) for each sub-field SFI-SFB, respectively.
FIG. 2 is a diagram representing an electrode arrangement in accordance with the related art, three electrode AC surface discharge PDP. Referring to FIG. 2, the related art three electrode AC surface discharge PDP includes scan electrodes Y1 to Yn and sustain electrodes Z which are formed in an upper plate, and address electrodes X1 to Xm, which are formed in a lower plate, and cross the scan electrodes Y1 to Yn and the sustain electrodes Z perpendicularly, as shown.
Discharge cells 1 for displaying any one of red, green and blue are arranged in a matrix at the intersections of the scan electrodes Y1 to Yn, the sustain electrode Z and the address electrodes X1 to Xm.
A dielectric layer and an MgO passivation layer (not shown) are deposited on the upper substrate where the scan electrodes Y1 to Yn and the sustain electrodes Z are formed.
Barrier ribs are formed on the lower substrate where the address electrodes X1 to Xm are formed, wherein the barrier ribs prevent optical and electrical crosstalk from occurring between the adjacent discharge cells. A phosphorus layer is formed on the surface of the lower plate and the barrier ribs, wherein the phosphorus is excited by ultraviolet rays to emit visible light.
Between the upper plate and the lower plate there is a discharge space. An inert gas mixture such as He+Xe, Ne+Xe and He+Xe+Ne is injected into the discharge space.
FIG. 3 is a diagram representing a driving waveform supplied to a PDP such as the PDP depicted in FIG. 2. Referring to FIG. 3, each of subfields SFn-1, SFn includes a reset period RP to initialize all of the discharge cells 1 across the entire screen, an address period AP to select certain discharge cells and a sustain period SP to sustain a discharge in those discharge cells 1 that were selected during the address period AP.
In a setup period SU of the reset period RP when nth subfield SFn starts, a positive(+) rising ramp waveform PR is applied to all the scan electrodes Y of the panel Cp, wherein the positive(+) rising ramp waveform PR rises from a sustain voltage Vs to a setup voltage Vsetup, and a ground voltage 0V is applied to the sustain electrodes Z and the address electrodes X. Hereby, in the discharge cells 1 across the entire screen, a dark discharge is generated, in which almost no light is emitted, between the scan electrodes Y and the address electrodes X of the panel Cp, and at the same time, a dark discharge is also generated between the scan electrodes Y and the sustain electrodes Z. As a result, positive(+) wall charges are left on the address electrodes X and the sustain electrodes Z and negative(−) wall charges are left on the scan electrode Y of the panel Cp, at the end of the setup period SU. While the dark discharge is generated in the setup period SU, a gap voltage Vg between the scan electrodes Y and the sustain electrodes Z of the panel Cp and a gap voltage Vg between the scan electrodes Y and the address electrodes X of the panel Cp is established, where the gap voltage Vg is close to a discharge firing voltage Vf, which is necessary to generate the discharge.
In a setdown period SD of the reset period RP subsequent to the setup period SU, a falling ramp waveform NR that falls from the sustain voltage Vs to a negative polarity(−) is applied to the scan electrodes Y of the panel Cp. At the same time, the positive(+) sustain voltage Vs is applied to the sustain electrodes Z and a ground voltage(0V) is applied to the address electrodes X. Hereby, a dark discharge is generated between the scan electrodes Y and the address electrodes X of the panel Cp within all of the discharge cells 1 across the entire screen, and almost at the same time, a dark discharge is generated between the scan electrodes Y and the sustain electrodes Z of the panel Cp. As a result, the wall charge distribution within each discharge cell 1 is changed to a condition which makes addressing possible. At this moment, excessive wall charges unnecessary for the address discharge are eliminated, and positive wall charges of a fixed amount are left on the scan electrodes Y and the address electrodes X of the panel Cp within each of the discharge cells 1. And, the wall charges on the sustain electrodes Z are inverted from the positive(+) polarity to the negative(−) polarity as the negative(−) wall charges moved from the scan electrodes Y of the panel Cp are accumulated. While the dark discharge is generated in the setdown period SD of the reset period RP, the gap voltage between the scan electrodes Y and the sustain electrodes Z of the panel Cp and the gap voltage between the scan electrodes Y and the address electrodes X come close to the discharge firing voltage Vf.
In the address period AP, a negative scan pulse −SCNP is sequentially applied to each of the scan electrodes Y, to Yn of the panel Cp, and for each scan electrode Y, a positive(+) data pulse DP is applied to select address electrodes X in synchronization with the scan pulse −SCNP. The voltage of the scan pulse −SCNP is a voltage that decreases from a negative(−) scan bias voltage Vscb, which is close to a ground voltage(0V), to a negative scan voltage −Vy. The voltage of the data pulse DP is a positive(+) data voltage Va. Further, during the address period AP, a positive(+) Z bias voltage Vzb which is lower than the positive(+) sustain voltage Vs is applied to the sustain electrodes Z. During the address period AP the gap voltage Vg between the scan electrodes Y and the address electrodes X of the panel Cp exceeds the discharge firing voltage Vf only within those cells that were selected (i.e., those cells for which a scan voltage Vsc and a data voltage Va were applied), to generate a first address discharge between the scan electrodes Y and the sustain electrodes Z of the panel Cp. Herein, the first address discharge of the scan electrodes Y and the address electrodes X of the panel Cp is generated at the vicinity of an edge which is far from the gap between the scan electrodes Y and the sustain electrodes Z of the panel Cp. The first address discharge of the scan electrodes Y and the address electrodes X of the panel Cp generates priming charged particles within the discharge cell to induce the scan electrodes Y and the sustain electrodes Z of the panel Cp.
On the other hand, the wall charge distribution within non-selected cells, where the address discharge is not generated, substantially remains at the same state as right after the setdown period SD.
In the sustain period SP, positive(+) sustain pulses SUSP are alternately applied to the scan electrodes Y and the sustain electrodes Z of the panel Cp. Then, the cells selected by the address discharge have a sustain discharge generated between the scan electrodes Y and the sustain electrodes Z of the panel Cp for each sustain pulse SUSP due to the wall charge distribution within the discharge cell which is formed as a result of the address discharge. On the contrary, in the non-selected cells, no discharge is generated during the sustain period. This is because the wall charge distribution in these cells remains at substantially the same state as right after the setdown period SD so that the gap voltage between the scan electrodes Y and the sustain electrodes Z of the panel Cp cannot exceed the discharge firing voltage Vf when the initial positive(+) sustain voltage Vs is applied to the scan electrodes Y. At this moment, the sustain pulses SUSP have the same voltage value as the sustain voltage Vs.
FIG. 4 is a diagram representing certain components in a related art plasma display panel.
Referring to FIG. 4, the related art plasma display panel includes a data driver 42 to supply data to address electrodes X1 to Xm; a scan driver 43 to drive scan electrodes Y1 to Yn; a sustain driver 44 to drive sustain electrodes Z; a timing controller to control each of the drivers 42, 43, 44; and a drive voltage generator 45 to supply the required drive voltages to each of the drivers 42, 43, 44.
The data driver 42 receives data which is mapped to each subfield by a subfield mapping circuit after they are reverse-gamma-corrected and error-diffused by a reverse gamma correction circuit and an error diffusion circuit (not shown). The data driver 42 samples and latches the data in response to a timing control signal from the timing control signal 41, and then it supplies the data voltage Va to the appropriate address electrodes X1 to Xm.
The scan driver 43 supplies initialization waveforms, as in FIG. 3, to the scan electrodes Y1 to Ym during the reset period RP under the control of the timing controller 41, and then supplies the scan bias voltage Vscb to the scan electrodes Y1 to Yn during the address period AP, and sequentially supplies the scan pulse −SCNP to the scan electrodes Y1 to Yn. And, the scan driver 43 supplies the sustain pulse SUSP to the scan electrodes Y1 to Ym during the sustain period under the control of the timing controller 41.
The sustain driver 44 supplies the positive(+) sustain voltage Vs and the positive(+) Z bias voltage Vzb to the sustain electrodes Z during the setdown period SD and the address period AP under the control of the timing controller 41, and then supplies the sustain pulse SUSP to the sustain electrodes Z by alternately operating the scan driver 43 during the sustain period.
The timing controller 41 receives a vertical/horizontal synchronization signal and a clock signal to generate timing control signals Cx, Cy, Cz required for each driver. It then supplies the timing control signals Cx, Cy, Cz to the corresponding drivers 42, 43, 44, thereby controlling the signals generated by each of the drivers 42, 43, 44. The data control signal Cx includes a sampling clock to sample the data, a latch control signal and a switch control signal to control the on/off time of a drive switch device and an energy recovery circuit within the data driver 42. The scan signal Cy includes a switch control signal to control the on/off time of a drive switch device and an energy recovery circuit within the scan driver 43. And the sustain control signal Cz includes a switch control signal to control the on/off time of a drive switch device and an energy recovery circuit within the sustain driver 44.
The drive voltage generator 45 generates a setup voltage Vsetup, a negative(−) scan voltage Vy, a DC bias voltage Vscb, Vzb, a positive(+) sustain voltage Vs and a data voltage Va.
FIG. 5 is a circuit diagram representing the scan driver 43 and the sustain driver 44 in detail. Referring to FIG. 5, the scan driver 43 includes a first energy recovery circuit 51, first to ninth switches SW1 to SW9 and a drive switch circuit 55. The sustain driver 44 includes a second energy recovery circuit 52 and twelfth and thirteenth switches SW12 and SW13.
The first and second energy recovery circuits 51 and 52 recover the reactive power energy, which does not contribute to the discharge in the PDP 40, from the scan electrode Y and the sustain electrode Z of the panel Cp and charges the scan electrode Y and the sustain electrode Z of the panel Cp using the recovered energy.
The drive switch circuit 55 includes tenth and eleventh switches SW10 and SW11 which are connected in a push-pull configuration between a third node N3 and a fourth node N4. An output terminal between the tenth and eleventh switch devices SW10, SW11 is connected to the scan electrode Y of the panel Cp.
The tenth switch SW10 is connected between the fourth node N4 and the scan electrode Y of the panel Cp to supply the voltage at node N4 to the scan electrode Y of the panel Cp through its body diode.
The eleventh switch SW11 is connected between the third node N3 and the scan electrode Y of the panel Cp to supply the voltage on the third node N3 to the scan electrode Y of the panel Cp through its body diode.
The first switch SW1 is connected between the sustain voltage source Vs and the first node N1 to supply the sustain voltage Vs to the first node N1 in accordance with a first switching control signal.
The second switch SW2 is connected between the ground voltage source GND and the first node N1 to supply the ground voltage GND to the first node N1 in accordance with a second switching control signal.
The third switch SW3 is connected between the first node N1 and the second node N2 to electrically connect the first node N1 with the second node N2 in accordance with a third switching control signal.
The fourth switch SW4 is connected between the setup voltage source Vsetup and the second node N2, and has its gate terminal connected to a first variable resistor R1. The fourth switch SW4 supplies a voltage, which rises to the setup voltage Vsetup with a designated slope in accordance with the change of the resistance value of the first variable resistor R1, to the second node N2 when a fourth switching control signal is supplied.
The fifth switch SW5 is connected between the second node N2 and the third node N3 to electrically connect the second node N2 with the third node N3 in accordance with a fifth switching control signal.
The sixth switch SW6 is connected between the third node N3 and the scan voltage source Vy, and has its gate terminal connected to a second variable resistor R2. The sixth switch SW6 supplies a voltage, which drops to the negative(−) scan voltage Vy with a designated slope in accordance with the change of the resistance value of the second variable resistor R2, to the third node N3 when a sixth switching control signal is supplied.
The seventh switch SW7 is connected between the third node N3 and the scan voltage source Vy to supply the negative(−) scan voltage Vy to the third node N3 in accordance with a fifth switching control signal.
The eighth switch SW8 is connected between the third node N3 and the fourth node N4 to electrically connect the third node N3 with the fourth node N4 in accordance with an eighth switching control signal.
The ninth switch SW9 is connected between the scan bias voltage source Vscb and the fourth node N4 to supply the scan bias voltage Vscb to the fourth node N4 in accordance with a ninth switching control signal.
The twelfth and thirteenth switches SW12 and SW13 are connected in series between the sustain voltage source Vs and the ground voltage source GND to supply the sustain voltage and the ground voltage to the sustain electrodes Z for the sustain period.
The switches SW1 to SW 13 are realized using field effect transistors (FET) which include embedded body diodes.
However, the related art scan driver 43, as shown in FIG. 6, induces a voltage at a gate terminal G, as shown in FIG. 7, as a current is charged/discharged through a parasitic capacitor between the drain terminal D and the gate terminal G of the sixth and seventh switches SW6, SW7 connected between the scan voltage source Vy and the third node N3, when the sustain pulse is applied to the scan electrode Y of the panel Cp because the negative(−) scan voltage source Vy is connected to the real ground, i.e., the ground voltage source GND. At this moment, if the voltage induced at the gate terminal G is higher than the threshold voltage of the FET associated with switch SW6, the sixth switch SW6 is abnormally turned on. This is a malfunction and, in the worst case, the sixth switch SW6 is destroyed. Further, the voltage induced at the gate terminal G not only increases the calorific temperature of the plasma display panel due to the parasitic capacitor C and the second parasitic resistor R2 connected to the gate terminal G, but it also increases power consumption.